# Create the VHDL model of a digital system that has outputs CC0 to CC7. Each output...

###### Question:

Create the VHDL model of a digital system that has outputs CC0 to CC7. Each output is active (logic 1) for one clock period in successive clock cycles. The outputs are all mutually exclusive when they are active, i.e. when one is logic I all others are logic 0. The block diagram and sample timing diagram of the system are shown below. After CC7 becomes logic 1, this pattern repeats by having CCO as logic 1 in the next clock cycle. The Reset input will take the system to an initial state where all outputs are zero. You may use behavioral or structural style of coding to develop the VHDL model. CLK еф Г Rext cca т cal CC2 -occ3 Cc4 CC ce2 CLK к нссе Сс hoca

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